1. Field of the Invention
Embodiments of the invention relate to nonvolatile semiconductor memory devices and related methods of operation.
2. Discussion of Related Art
Generally, read and write (programming/erase) operations for memory cells in a nonvolatile semiconductor memory device are carried out by controlling bit line voltages corresponding to selected memory cells. In order to properly drive bit lines voltages during a read or programming operation, contemporary nonvolatile semiconductor memory devices provide one or more input/output circuits to temporarily store the data to be written into or read from the memory cells.
FIG. 1 is a diagram illustrating a conventional nonvolatile semiconductor memory device. As shown, the device includes a memory cell array 10. The memory cell array 10 comprises a plurality of even and odd grouped bit lines (BLe<n:1> and BLo<n:1>), and corresponding strings St of memory cells for storing data received from bit lines (BLe<n:1> and BLo<n:1>) and outputting read data to the bit lines (BLe<n:1> and BLo<n:1>). Each pair of bit lines BLe and BLo is connected to an input/output circuit 20.
FIG. 2 illustrates a portion of the memory cells in the memory cell array 10 in some additional detail. As shown, the memory cell array 10 comprises a plurality of cell strings (Ste<n:1> and STo<n:1>) each respectively connected to one of the bit lines (BLe<n:1> and BLo<n:1>). Each cell string in the illustrated example is formed from a string selection transistor (SST) connected to its corresponding bit line, a ground selection transistor (GST) connected to a common source line (CSL), and a plurality of memory cells (MC) connected in series between the string selection transistor (SST) and the ground selection transistor (GST). As shown in FIG. 1, more than one string may be connected to a bit line (FIG. 2 shows only one string per bit line for clarity).
Each one of the memory cells (MC) comprises a floating-gate transistor having a source, a drain, a floating gate and a control gate. The memory cells (MC) may be programmed using the Channel Hot Electron (CHE) effect or the Fowler-Nordheim (F-N) tunneling effect. These techniques are both conventionally understood.
As shown in FIG. 1, two adjacent bit lines are configured to constitute a pair of bit lines. However, each bit line may be selected in relation to a unique column address. Therefore, in this disclosure the two bit lines, (i.e., an even bit line and an odd bit line) may be referred to individually or collectively as a “bit line” without further differentiation.
FIG. 1 further shows that the memory device includes a row selector 510 and control logic 500. The control logic 500 receives command and address information (e.g., from a host system), and generates control signals to control the operation of the row selector 510 and the input/output circuits 20. The commands may be at least one of a read command and a write command. The address information indicates an address of at least one memory cell in the memory cell array 10. In particular, the control logic 500 decodes the address information into a row address and a column address.
Based on the command and the row address, the control logic 500 controls the row selector 510 to assert the appropriate word lines WLi, string selection transistor (SST) and a ground selection transistor (GST) to select a row of memory cells MC for a read or write operation. Based on the command and the column address, the control logic 500 generates the control signals supplied to the input/output circuits 20 as described in detail below.
As shown in FIG. 1, each input/output circuit 20 includes a bit line biasing and coupling circuit 110, a bit line blocking circuit 120, a page buffer 150 and a column gate 160. Data to be written to a selected memory cell is supplied on a data input line 300. The data is loaded and latched in the page buffer 150 via the associated column gate 160. Data stored in the page buffer 150 is thus provided to bit line BLe or BLo through the bit line (BL) blocking circuit 120 and the BL bias and coupling circuit 110. Thereafter, a programming operation may be performed relative to the selected memory cell. In similar fashion, data read from a selected memory cell is transferred via the BL bias and coupling circuit 110 and the BL blocking circuit 120, and temporarily stored in the page buffer 150. Data thus stored in page buffer 150 may be transferred to an output data line 200 in response to a column gate signal applied to the column gate 160 by the control logic 500.
FIG. 3 illustrates the circuits comprising the input/output circuit 20 in greater detail. As shown, the bit line biasing and coupling circuit 110 includes first and second high voltage transistors 112 and 114 connected in series between the even and odd bit lines BLe and BL0. The node connecting the first and second high voltage transistors 112 and 114 receives a bit line bias BLPWR. As will be appreciated, the bit line bias BLPWR is, generally, either a reference ground voltage Vss or a power supply voltage Vdd. First and second control signals SHLDe and SHLDo are supplied to the gates of the first and second high voltage transistors 112 and 114.
Because, in this example, the first and second high voltage transistors 112 and 114 are NMOS transistors, if the first and second control signals SHLDen and SHLDo are high, then the bit line bias BLPWR is supplied to the even and odd bit lines BLe and BLo to, for example, pre-charge the bit lines. If the first and second control signals SHLDe and SHLDo are low, then the then the bit line bias BLPWR is not supplied to the even and odd bit lines BLe and BLo. In view of the function of the first and second high voltage transistors 112 and 114, these transistors are often referred to as pre-charge transistors because they are used to pre-charge the bit lines.
The bit line biasing and coupling circuit 110 also includes a third high voltage transistor 116 connected to the even bit line BLe and a fourth high voltage transistor 118 connected to the odd bit line BLo. The outputs of the third and fourth high voltage transistors 116 and 118 are connected together and to the bit line blocking circuit 120. The third and fourth high voltage transistors 116 and 118 receive third and fourth control signals BLSLTe and BLSLTo at their gates, respectively. When the third and fourth control signals BLSLTe and BLSLTo are high, the third and fourth high voltage transistors 116 and 118 couple the even and odd bit lines BLe and BLo to the blocking circuit 120. When the third and fourth control signals BLSLTe and BLSLTo are low, the third and fourth high voltage transistors 116 and 118 de-couple the even and odd bit lines BLe and BLo from the blocking circuit 120. As a result, the third and fourth high voltage transistors 116 and 118 are also commonly referred to as de-coupling transistors.
As shown in FIG. 3, the blocking circuit 120 includes a single high voltage transistor connecting the bit line bias and coupling circuit 110 to the page buffer 150. The high voltage blocking transistor 120 receives a fifth control signal SOBLK at its gate. When the fifth control signal SOBLK is high, the high voltage blocking transistor 120 connects the bit line bias and coupling circuit 110 with the page buffer 150. When the fifth control signal SOBLK is low, the high voltage blocking transistor 120 blocks the connection between the bit line bias and coupling circuit 110 and the page buffer 150.
FIG. 3 further shows the details of the page buffer 150. Because the page buffer 150 shown in FIG. 3 is so well known it will not be described in detail for the sake of brevity. It is sufficient to note that the page buffer 150 does include a latch 152 for temporarily storing input or output data with respect to the memory cell array 10.
Also, as further shown in FIG. 3 the column gate 160 includes a transistor connecting the page buffer 150 to the input data line 300 and the output data line 200. The column gate transistor 160 receives a column gate signal YG at its gate. When the column gate signal is high, the input data line 300 and the output data line 200 are connected with the page buffer 150. When the column gate signal YG is low, the input data line 300 and the output data line 200 are disconnected with the page buffer 150.
FIG. 3 further provides an indication of the layout architecture of the memory cell array 10 and the input/output circuit 20. As shown, FIG. 3 indicates that the memory cell array 10 is formed in a cell array or pocket-Pwell region 600 of a semiconductor substrate while the input/output circuit 20 is formed over a high voltage transistor region 700 and a low voltage transistor region 800. More specifically, the bit line bias and coupling circuit 110 and the bit line blocking circuit 120, which include high voltage transistors are formed in a high voltage transistor region 700 of the semiconductor substrate. By contrast, the page buffer 150 and column gate 160 are formed in a low voltage transistor region 800 of the semiconductor substrate.
FIG. 4 illustrates a cross-sectional perspective view of the layout architecture of the memory cell array 10 and input/output circuit 20 shown in FIG. 3. It will be understood that the layout architecture shown in FIG. 4 is not a true cross-section of the semiconductor substrate, but instead, is a side view of the semiconductor substrate. Furthermore it will be understood, that for the sake of clarity, many details to create an operational circuit layout have not been shown. Namely, FIG. 4 is a graphical representation (e.g., the low voltage transistor region 800 including the page buffer 150 has been represented as the Nwell 804 and Pwell 802). Still further, the processing steps and techniques to produce the layout architecture shown in FIG. 4 will not be described as these are well-known and readily understood from FIG. 4. As shown in FIG. 4, a p-type substrate 900 has an N-type well 602 formed therein. A pocket-Pwell 600 is formed in the Nwell 602. The pocket-Pwell (P-Pwell) 600 defines the cell array or pocket-Pwell region 600, and the memory cell transistors are formed in this pocket-Pwell region 600.
FIG. 4 also shows that a Pwell 802 and Nwell 804 are formed in the substrate 900 disposed away from the Nwell region 602. The Pwell region 802 and Nwell region 804 form the low voltage transistor region 800. As graphically shown in FIG. 4, it is in this region that transistors are formed to create the page buffer 150, column gate 160, etc.
The p-type substrate 900 disposed between the Pwell 802 and the Nwell 602 is where the high voltage transistors of the bit line biasing and coupling circuit 110 and the blockining circuit 120 are formed. Namely, the portion of the p-type substrate 900 disposed between the Pwell 802 and the Nwell 602 forms the high voltage transistor region 700. FIG. 4 shows the second, fourth and blocking high voltage transistors 114, 118 and 120 in the high voltage region 700. While FIG. 4 has not been drawn to scale, FIG. 4 does illustrate the size relationship between the transistors formed in the different regions. Namely, FIG. 4 shows that the high voltage transistors, because of their need to transfer and block high voltages, are significantly greater in size then the transistors in the low voltage transistor region 800 or the transistors in the cell array region 600. As a result, a significant portion of the substrate 900 is devoted towards the high voltage transistor region 700.
As mentioned above, the high voltage transistors and the high voltage transistor region 700 are formed relatively large as a result of the high voltages they must withstand during operation. FIG. 5 illustrates an example of an erase operation and the high voltages incurred by the high voltage transistors and the high voltage transistor region 700. As shown, during an erase operation, an erase voltage of about 20 volts is induced on the bit lines BLe and BLo as a result of the pocket-Pwell 600 being biased to 20 volts. However, the gates of the high voltage bit line biasing transistors 112 and 114 are supplied with zero volts to prevent the 20 volt bias from being transferred out upon the conductor upon which the bias control signal BLPWR is received. As shown in FIG. 5, this creates great stress in the high voltage pre-charge transistors 112 and 114, and necessitates their large size.
As further shown in FIG. 5, 20 volts is applied to the gates of the high voltage de-coupling transistors 116 and 118 such that these transistors transfer the 20 volts received along the bit lines BLe and BLo. As shown in FIG. 5, transferring such a high voltage also induces great stress in these transistors, and necessitates the large size of the high voltage de-coupling transistors 116 and 118. The 20 volts transferred by the high voltage de-coupling transistors 116 and 118 is supplied to the high voltage blocking transistor 120, which receives the power supply voltage VDD at its gate. The high voltage blocking transistor 120 throttles the voltage received, such that only a threshold difference of the power supply voltage reaches the low voltage transistor region 800.